Design automation for integrated circuits, particularly application specific integrated circuits (ASICs), is becoming increasingly important as the integrated circuits become more complex and dense. Design modeling, layout and verification of these integrated circuits, for example, are becoming more mathematically complex and time intensive. Any reduction in the complexity or time intensity would favorably reduce the period between device design and prototype.
A typical design process begins by entering the integrated circuit design in a hardware description language, such as VHDL. An industry standard CAE platform is used, such as Mentor Graphics Design Architect, Synopsys Design Analyzer or Cadence Verilog. The designer of the integrated circuit usually enters the design of the integrated circuit's surrounding environment or architecture. The surrounding environment or architecture is known as a "test bench." The test bench and integrated circuit together form a "system."
To conceptually illustrate the description above, reference is made to FIG. 1. A system 110 is shown which includes a test bench 120 and a device design 130. Test bench 120 and device design 130 interact with signals provided through signal paths 125 and 135. System 110 of FIG. 1 is implemented as software for use on a CAE platform.
Using the "Test Bench" methodology allows the designer to simulate a new device while using the capabilities of the simulator to generate input stimulus based on programmed simulation data and feedback from the device under test. The simulation is performed by creating a test bench that imitates the behavior of the system in which the device being designed will operate. As the simulation runs, input stimulus is applied to the device and outputs are monitored. During the simulation run, input stimulus to the device and output signals from the device are recorded in a simulation output file. Once the simulation has ended this simulation output file is analyzed to ensure tester timing and format constraints have not been violated as well as to ensure the device performed functionally as expected.
After analysis, if no errors are detected, test vectors are extracted from the simulation results. The design is subsequently implemented as a physical integrated circuit device. The physical device is tested by using automatic test equipment (ATE). The ATE tests the physical device by applying signals to the device according to the extracted test vectors and comparing output states from the device against expected output states specified by the test vectors extracted from the simulation output.
An inherent problem with the above described process is that the simulators used to simulate designs offer more flexibility with respect to signal formats and timings than the ATE used for the physical device test. Specifically, a simulation is a software representation of the real world, and with no restrictions is capable of creating signal formats that are beyond the ability of ATE to reproduce. In a manufacturing test environment it is important for the ATE to be able to reproduce the waveforms exactly as they were simulated to ensure that the test will operate correctly and produce the expected results.
To illustrate, all ATE have a physical limitation to their maximum test frequency or clock rate. Also, ATE usually support a limited set of signal formats or a maximum number of input transitions in a period. In contrast, the simulator is not limited in these ways, and arbitrary signal formats can be created and frequencies well beyond the capabilities of ATE can be simulated.
The lesser flexibility of the ATE compared to the CAE often causes problems for integrated circuit designers. For example, if a designer defines a signal with jitter for a simulation input stimulus, that jitter may cause inaccurate test vector extraction although the simulation operated as expected. This is a problem when considered in light of the amount of time simulations require. A typical ASIC design can require anywhere from a few hours to a few days of simulation run time on a computer or work station. Errors uncovered by the analysis in many cases will require changes be made to the simulation input stimulus and subsequent resimulation. If errors are not caught at this stage and test vectors are extracted from the resultant output of the simulation it could be several weeks before the vectors are used by the ATE to test the physical device. If the test vectors are inaccurate, then the ATE may fail good parts or pass bad parts. Hence, a new cycle of simulation extraction and ATE testing must be done. This time loss is unacceptable to most ASIC customers.
To overcome this problem, a common requirement is that the timings and signal formats that comprise the input stimulus for the simulation must conform to specifications defined by a target ATE that will be used to test the actual physical device. A simulation from such conforming stimulus is said to be "tester compatible."
In order to generate tester compatible stimulus, the designer must manually define the test bench/device interface to produce signals that conform to the restricted timing constraints of the targeted ATE. Since simulation takes a considerable amount of time, it would be beneficial for designers to know that their test benches will produce correct signals before investing the time and resources to simulate the device.
In many cases IC design packages provide a device database that requires the user to define the signal formats and timings. This database is checked against ATE specifications to ensure that the timing information is tester compatible. In addition, timing and format information from this database is used to verify the results of the simulation after it is performed.
A need exists for automatically providing test vectors that accurately represent simulation stimulus while conforming to ATE constraints. The present invention meets this need.